/***********************************************************************/
/*                                                                     */
/*  FILE        :intprg.c                                              */
/*  DATE        :Wed, May 07, 2003                                     */
/*  DESCRIPTION :Interrupt Program                                     */
/*  CPU TYPE    :SH7055F                                               */
/*                                                                     */
/*  This file is generated by Hitachi Project Generator (Ver.1.2).     */
/*                                                                     */
/***********************************************************************/
                  


#include <machine.h>
#include "vect.h"
#pragma section IntPRG
// 4 Illegal code
void INT_Illegal_code(void){/* sleep(); */}
// 5 Reserved

// 6 Illegal slot
void INT_Illegal_slot(void){/* sleep(); */}
// 7 Reserved

// 8 Reserved

// 9 CPU Address error
void INT_CPU_Address(void){/* sleep(); */}
// 10 DMAC Address error
void INT_DMAC_Address(void){/* sleep(); */}
// 11 NMI
void INT_NMI(void){/* sleep(); */}
// 12 User breakpoint trap
void INT_User_Break(void){/* sleep(); */}
// 13 FPU
void INT_FPU(void){/* sleep(); */}
// 14 H-UDI
void INT_HUDI(void){/* sleep(); */}
// 15 Reserved

// 16 Reserved

// 17 Reserved

// 18 Reserved

// 19 Reserved

// 20 Reserved

// 21 Reserved

// 22 Reserved

// 23 Reserved

// 24 Reserved

// 25 Reserved

// 26 Reserved

// 27 Reserved

// 28 Reserved

// 29 Reserved

// 30 Reserved

// 31 Reserved

// 32 TRAPA (User Vecter)
void INT_TRAPA32(void){/* sleep(); */}
// 33 TRAPA (User Vecter)
void INT_TRAPA33(void){/* sleep(); */}
// 34 TRAPA (User Vecter)
void INT_TRAPA34(void){/* sleep(); */}
// 35 TRAPA (User Vecter)
void INT_TRAPA35(void){/* sleep(); */}
// 36 TRAPA (User Vecter)
void INT_TRAPA36(void){/* sleep(); */}
// 37 TRAPA (User Vecter)
void INT_TRAPA37(void){/* sleep(); */}
// 38 TRAPA (User Vecter)
void INT_TRAPA38(void){/* sleep(); */}
// 39 TRAPA (User Vecter)
void INT_TRAPA39(void){/* sleep(); */}
// 40 TRAPA (User Vecter)
void INT_TRAPA40(void){/* sleep(); */}
// 41 TRAPA (User Vecter)
void INT_TRAPA41(void){/* sleep(); */}
// 42 TRAPA (User Vecter)
void INT_TRAPA42(void){/* sleep(); */}
// 43 TRAPA (User Vecter)
void INT_TRAPA43(void){/* sleep(); */}
// 44 TRAPA (User Vecter)
void INT_TRAPA44(void){/* sleep(); */}
// 45 TRAPA (User Vecter)
void INT_TRAPA45(void){/* sleep(); */}
// 46 TRAPA (User Vecter)
void INT_TRAPA46(void){/* sleep(); */}
// 47 TRAPA (User Vecter)
void INT_TRAPA47(void){/* sleep(); */}
// 48 TRAPA (User Vecter)
void INT_TRAPA48(void){/* sleep(); */}
// 49 TRAPA (User Vecter)
void INT_TRAPA49(void){/* sleep(); */}
// 50 TRAPA (User Vecter)
void INT_TRAPA50(void){/* sleep(); */}
// 51 TRAPA (User Vecter)
void INT_TRAPA51(void){/* sleep(); */}
// 52 TRAPA (User Vecter)
void INT_TRAPA52(void){/* sleep(); */}
// 53 TRAPA (User Vecter)
void INT_TRAPA53(void){/* sleep(); */}
// 54 TRAPA (User Vecter)
void INT_TRAPA54(void){/* sleep(); */}
// 55 TRAPA (User Vecter)
void INT_TRAPA55(void){/* sleep(); */}
// 56 TRAPA (User Vecter)
void INT_TRAPA56(void){/* sleep(); */}
// 57 TRAPA (User Vecter)
void INT_TRAPA57(void){/* sleep(); */}
// 58 TRAPA (User Vecter)
void INT_TRAPA58(void){/* sleep(); */}
// 59 TRAPA (User Vecter)
void INT_TRAPA59(void){/* sleep(); */}
// 60 TRAPA (User Vecter)
void INT_TRAPA60(void){/* sleep(); */}
// 61 TRAPA (User Vecter)
void INT_TRAPA61(void){/* sleep(); */}
// 62 TRAPA (User Vecter)
void INT_TRAPA62(void){/* sleep(); */}
// 63 TRAPA (User Vecter)
void INT_TRAPA63(void){/* sleep(); */}
// 64 Interrupt IRQ0
void INT_IRQ0(void){/* sleep(); */}
// 65 Interrupt IRQ1
void INT_IRQ1(void){/* sleep(); */}
// 66 Interrupt IRQ2
void INT_IRQ2(void){/* sleep(); */}
// 67 Interrupt IRQ3
void INT_IRQ3(void){/* sleep(); */}
// 68 Interrupt IRQ4
void INT_IRQ4(void){/* sleep(); */}
// 69 Interrupt IRQ5
void INT_IRQ5(void){/* sleep(); */}
// 70 Interrupt IRQ6
void INT_IRQ6(void){/* sleep(); */}
// 71 Interrupt IRQ7
void INT_IRQ7(void){/* sleep(); */}
// 72 DMAC0 DEI0
void INT_DMAC0_DEI0(void){/* sleep(); */}
// 73 Reserved 

// 74 DMAC1 DEI1
void INT_DMAC1_DEI1(void){/* sleep(); */}
// 75 Reserved

// 76 DMAC2 DEI2
void INT_DMAC2_DEI2(void){/* sleep(); */}
// 77 Reserved

// 78 DMAC3 DEI3
void INT_DMAC3_DEI3(void){/* sleep(); */}
// 79 Reserved

// 80 ATU01 ITV0-2
void INT_ATU01_ITV(void){/* sleep(); */}
// 81 Reserved

// 82 Reserved

// 83 Reserved

// 84 ATU02 ICI0A
void INT_ATU02_ICI0A(void){/* sleep(); */}
// 85 Reserved

// 86 ATU02 ICI0B
void INT_ATU02_ICI0B(void){/* sleep(); */}
// 87 Reserved

// 88 ATU03 ICI0C
void INT_ATU03_ICI0C(void){/* sleep(); */}
// 89 Reserved

// 90 ATU03 ICI0D
void INT_ATU03_ICI0D(void){/* sleep(); */}
// 91 Reserved

// 92 ATU04 OVI0
void INT_ATU04_OVI0(void){/* sleep(); */}
// 93 Reserved

// 94 Reserved

// 95 Reserved

// 96 ATU11 IMI1AA/CMI1BA
void INT_ATU11_IMI1AA(void){/* sleep(); */}
// 97 ATU11 IMI1AB
void INT_ATU11_IMI1AB(void){/* sleep(); */}
// 98 ATU11 IMI1AC
void INT_ATU11_IMI1AC(void){/* sleep(); */}
// 99 ATU11 IMI1AD
void INT_ATU11_IMI1AD(void){/* sleep(); */}
// 100 ATU12 IMI1AE
void INT_ATU12_IMI1AE(void){/* sleep(); */}
// 101 ATU12 IMI1AF
void INT_ATU12_IMI1AF(void){/* sleep(); */}
// 102 ATU12 IMI1AG
void INT_ATU12_IMI1AG(void){/* sleep(); */}
// 103 ATU12 IMI1AH
void INT_ATU12_IMI1AH(void){/* sleep(); */}
// 104 ATU13 OVI1A-OVI1B
void INT_ATU13_OVI1(void){/* sleep(); */}
// 105 Reserved

// 106 Reserved

// 107 Reserved

// 108 ATU21 IMI2A
void INT_ATU21_IMI2A(void){/* sleep(); */}
// 109 ATU21 IMI2B
void INT_ATU21_IMI2B(void){/* sleep(); */}
// 110 ATU21 IMI2C
void INT_ATU21_IMI2C(void){/* sleep(); */}
// 111 ATU21 IMI2D
void INT_ATU21_IMI2D(void){/* sleep(); */}
// 112 ATU22 IMI2E
void INT_ATU22_IMI2E(void){/* sleep(); */}
// 113 ATU22 IMI2F
void INT_ATU22_IMI2F(void){/* sleep(); */}
// 114 ATU22 IMI2G
void INT_ATU22_IMI2G(void){/* sleep(); */}
// 115 ATU22 IMI2H
void INT_ATU22_IMI2H(void){/* sleep(); */}
// 116 ATU23 OVI2A-OVI2B
void INT_ATU23_OVI2(void){/* sleep(); */}
// 117 Reserved

// 118 Reserved

// 119 Reserved

// 120 ATU31 IMI3A
void INT_ATU31_IMI3A(void){/* sleep(); */}
// 121 ATU31 IMI3B
void INT_ATU31_IMI3B(void){/* sleep(); */}
// 122 ATU31 IMI3C
void INT_ATU31_IMI3C(void){/* sleep(); */}
// 123 ATU31 IMI3D
void INT_ATU31_IMI3D(void){/* sleep(); */}
// 124 ATU32 OVI3
void INT_ATU32_OVI3(void){/* sleep(); */}
// 125 Reserved

// 126 Reserved

// 127 Reserved

// 128 ATU41 IMI4A
void INT_ATU41_IMI4A(void){/* sleep(); */}
// 129 ATU41 IMI4B
void INT_ATU41_IMI4B(void){/* sleep(); */}
// 130 ATU41 IMI4C
void INT_ATU41_IMI4C(void){/* sleep(); */}
// 131 ATU41 IMI4D
void INT_ATU41_IMI4D(void){/* sleep(); */}
// 132 ATU42 OVI4
void INT_ATU42_OVI4(void){/* sleep(); */}
// 133 Reserved

// 134 Reserved

// 135 Reserved

// 136 ATU51 IMI5A
void INT_ATU51_IMI5A(void){/* sleep(); */}
// 137 ATU51 IMI5B
void INT_ATU51_IMI5B(void){/* sleep(); */}
// 138 ATU51 IMI5C
void INT_ATU51_IMI5C(void){/* sleep(); */}
// 139 ATU51 IMI5D
void INT_ATU51_IMI5D(void){/* sleep(); */}
// 140 ATU52 OVI5
void INT_ATU52_OVI5(void){/* sleep(); */}
// 141 Reserved

// 142 Reserved

// 143 Reserved

// 144 ATU6 IMI6A
void INT_ATU6_IMI6A(void){/* sleep(); */}
// 145 ATU6 IMI6B
void INT_ATU6_IMI6B(void){/* sleep(); */}
// 146 ATU6 IMI6C
void INT_ATU6_IMI6C(void){/* sleep(); */}
// 147 ATU6 IMI6D
void INT_ATU6_IMI6D(void){/* sleep(); */}
// 148 ATU7 IMI7A
void INT_ATU7_IMI7A(void){/* sleep(); */}
// 149 ATU7 IMI7B
void INT_ATU7_IMI7B(void){/* sleep(); */}
// 150 ATU7 IMI7C
void INT_ATU7_IMI7C(void){/* sleep(); */}
// 151 ATU7 IMI7D
void INT_ATU7_IMI7D(void){/* sleep(); */}
// 152 ATU81 OSI8A
void INT_ATU81_OSI8A(void){/* sleep(); */}
// 153 ATU81 OSI8B
void INT_ATU81_OSI8B(void){/* sleep(); */}
// 154 ATU81 OSI8C
void INT_ATU81_OSI8C(void){/* sleep(); */}
// 155 ATU81 OSI8D
void INT_ATU81_OSI8D(void){/* sleep(); */}
// 156 ATU82 OSI8E
void INT_ATU82_OSI8E(void){/* sleep(); */}
// 157 ATU82 OSI8F
void INT_ATU82_OSI8F(void){/* sleep(); */}
// 158 ATU82 OSI8G
void INT_ATU82_OSI8G(void){/* sleep(); */}
// 159 ATU82 OSI8H
void INT_ATU82_OSI8H(void){/* sleep(); */}
// 160 ATU83 OSI8I
void INT_ATU83_OSI8I(void){/* sleep(); */}
// 161 ATU83 OSI8J
void INT_ATU83_OSI8J(void){/* sleep(); */}
// 162 ATU83 OSI8K
void INT_ATU83_OSI8K(void){/* sleep(); */}
// 163 ATU83 OSI8L
void INT_ATU83_OSI8L(void){/* sleep(); */}
// 164 ATU84 OSI8M
void INT_ATU84_OSI8M(void){/* sleep(); */}
// 165 ATU84 OSI8N
void INT_ATU84_OSI8N(void){/* sleep(); */}
// 166 ATU84 OSI8O
void INT_ATU84_OSI8O(void){/* sleep(); */}
// 167 ATU84 OSI8P
void INT_ATU84_OSI8P(void){/* sleep(); */}
// 168 ATU91 CMI9A
void INT_ATU91_CMI9A(void){/* sleep(); */}
// 169 ATU91 CMI9B
void INT_ATU91_CMI9B(void){/* sleep(); */}
// 170 ATU91 CMI9C
void INT_ATU91_CMI9C(void){/* sleep(); */}
// 171 ATU91 CMI9D
void INT_ATU91_CMI9D(void){/* sleep(); */}
// 172 ATU92 CMI9E
void INT_ATU92_CMI9E(void){/* sleep(); */}
// 173 Reserved

// 174 ATU92 CMI9F
void INT_ATU92_CMI9F(void){/* sleep(); */}
// 175 Reserved

// 176 ATU101 CMI10A
void INT_ATU101_CMI10A(void){/* sleep(); */}
// 177 Reserved

// 178 ATU101 CMI10B
void INT_ATU101_CMI10B(void){/* sleep(); */}
// 179 Reserved

// 180 ATU102 IMI10AG
void INT_ATU102_IMI10AG(void){/* sleep(); */}
// 181 Reserved

// 182 Reserved

// 183 Reserved

// 184 ATU11 IMI11A
void INT_ATU11_IMI11A(void){/* sleep(); */}
// 185 Reserved

// 186 ATU11 IMI11B
void INT_ATU11_IMI11B(void){/* sleep(); */}
// 187 ATU11 OVI1
void INT_ATU11_OVI1(void){/* sleep(); */}
// 188 CMT0 CMTI0
void INT_CMT0_CMTI0(void){/* sleep(); */}
// 189 Reserved

// 190 A/D0 ADI0
void INT_ADI0(void){/* sleep(); */}
// 191 Reserved

// 192 CMT1 CMTI1
void INT_CMT1_CMTI1(void){/* sleep(); */}
// 193 Reserved

// 194 A/D1 ADI1
void INT_AD1_ADI1(void){/* sleep(); */}
// 195 Reserved

// 196 A/D2 ADI2
void INT_AD2_ADI2(void){/* sleep(); */}
// 197 Reserved

// 198 Reserved

// 199 Reserved

// 200 SCI0 ERI0
void INT_SCI0_ERI0(void){/* sleep(); */}
// 201 SCI0 RXI0
void INT_SCI0_RXI0(void){/* sleep(); */}
// 202 SCI0 TXI0
void INT_SCI0_TXI0(void){/* sleep(); */}
// 203 SCI0 TEI0
void INT_SCI0_TEI0(void){/* sleep(); */}
// 204 SCI1 ERI1
void INT_SCI1_ERI1(void){/* sleep(); */}
// 205 SCI1 RXI1
void INT_SCI1_RXI1(void){/* sleep(); */}
// 206 SCI1 TXI1
void INT_SCI1_TXI1(void){/* sleep(); */}
// 207 SCI1 TEI1
void INT_SCI1_TEI1(void){/* sleep(); */}
// 208 SCI2 ERI2
void INT_SCI2_ERI2(void){/* sleep(); */}
// 209 SCI2 RXI2
void INT_SCI2_RXI2(void){/* sleep(); */}
// 210 SCI2 TXI2
void INT_SCI2_TXI2(void){/* sleep(); */}
// 211 SCI2 TEI2
void INT_SCI2_TEI2(void){/* sleep(); */}
// 212 SCI3 ERI3
void INT_SCI3_ERI3(void){/* sleep(); */}
// 213 SCI3 RXI3
void INT_SCI3_RXI3(void){/* sleep(); */}
// 214 SCI3 TXI3
void INT_SCI3_TXI3(void){/* sleep(); */}
// 215 SCI3 TEI3
void INT_SCI3_TEI3(void){/* sleep(); */}
// 216 SCI4 ERI4
void INT_SCI4_ERI4(void){/* sleep(); */}
// 217 SCI4 RXI4
void INT_SCI4_RXI4(void){/* sleep(); */}
// 218 SCI4 TXI4
void INT_SCI4_TXI4(void){/* sleep(); */}
// 219 SCI4 TEI4
void INT_SCI4_TEI4(void){/* sleep(); */}
// 220 HCAN0 ERS0
void INT_HCAN0_ERS0(void){/* sleep(); */}
// 221 HCAN0 OVR0
void INT_HCAN0_OVR0(void){/* sleep(); */}
// 222 HCAN0 RM0
void INT_HCAN0_RM0(void){/* sleep(); */}
// 223 HCAN0 SLE0
void INT_HCAN0_SLE0(void){/* sleep(); */}
// 224 WDT ITI
void INT_WDT_ITI(void){/* sleep(); */}
// 225 Reserved

// 226 Reserved

// 227 Reserved

// 228 HCAN1 ERS1
void INT_HCAN1_ERS1(void){/* sleep(); */}
// 229 HCAN1 OVR1
void INT_HCAN1_OVR1(void){/* sleep(); */}
// 230 HCAN1 RM1
void INT_HCAN1_RM1(void){/* sleep(); */}
// 231 HCAN1 SLE1
void INT_HCAN1_SLE1(void){/* sleep(); */}
// 232 Reserved

// 233 Reserved

// 234 Reserved

// 235 Reserved

// 236 Reserved

// 237 Reserved

// 238 Reserved

// 239 Reserved

// 240 Reserved

// 241 Reserved

// 242 Reserved

// 243 Reserved

// 244 Reserved

// 245 Reserved

// 246 Reserved

// 247 Reserved

// 248 Reserved

// 249 Reserved

// 250 Reserved

// 251 Reserved

// 252 Reserved

// 253 Reserved

// 254 Reserved

// 255 Reserved


// Dummy
void Dummy(void){/* sleep(); */}
