/***********************************************************************/
/*                                                                     */
/*  FILE        :vecttbl.c                                             */
/*  DATE        :Wed, Apr 30, 2003                                     */
/*  DESCRIPTION :Initialize of Vector Table                            */
/*  CPU TYPE    :SH7055F                                               */
/*                                                                     */
/*  This file is generated by Hitachi Project Generator (Ver.1.2).     */
/*                                                                     */
/***********************************************************************/
                  


#include "vect.h"

#pragma section VECTTBL

void *RESET_Vectors[] = {
//;<<VECTOR DATA START (POWER ON RESET)>>
//;0 Power On Reset PC
    (void*)	PowerON_Reset_PC,                                                                                                                
//;<<VECTOR DATA END (POWER ON RESET)>>
// 1 Power On Reset SP
    (void*) &PowerON_Reset_SP,
//;<<VECTOR DATA START (MANUAL RESET)>>
//;2 Manual Reset PC
    (void*)	Manual_Reset_PC,                                                                                                                 
//;<<VECTOR DATA END (MANUAL RESET)>>
// 3 Manual Reset SP
    (void*) &Manual_Reset_SP

};
/*
#pragma section INTTBL
void *INT_Vectors[] = {
// 4 Illegal code
    (void*) INT_Illegal_code,
// 5 Reserved
    (void*) Dummy,
// 6 Illegal slot
    (void*) INT_Illegal_slot,
// 7 Reserved
    (void*) Dummy,
// 8 Reserved
    (void*) Dummy,
// 9 CPU Address error
    (void*) INT_CPU_Address,
// 10 DMAC Address error
    (void*) INT_DMAC_Address,
// 11 NMI
    (void*) INT_NMI,
// 12 User breakpoint trap
    (void*) INT_User_Break,
// 13 FPU
    (void*) INT_FPU,
// 14 H-UDI
    (void*) INT_HUDI,
// 15 Reserved
    (void*) Dummy,
// 16 Reserved
    (void*) Dummy,
// 17 Reserved
    (void*) Dummy,
// 18 Reserved
    (void*) Dummy,
// 19 Reserved
    (void*) Dummy,
// 20 Reserved
    (void*) Dummy,
// 21 Reserved
    (void*) Dummy,
// 22 Reserved
    (void*) Dummy,
// 23 Reserved
    (void*) Dummy,
// 24 Reserved
    (void*) Dummy,
// 25 Reserved
    (void*) Dummy,
// 26 Reserved
    (void*) Dummy,
// 27 Reserved
    (void*) Dummy,
// 28 Reserved
    (void*) Dummy,
// 29 Reserved
    (void*) Dummy,
// 30 Reserved
    (void*) Dummy,
// 31 Reserved
    (void*) Dummy,
// 32 TRAPA (User Vecter)
    (void*) INT_TRAPA32,
// 33 TRAPA (User Vecter)
    (void*) INT_TRAPA33,
// 34 TRAPA (User Vecter)
    (void*) INT_TRAPA34,
// 35 TRAPA (User Vecter)
    (void*) INT_TRAPA35,
// 36 TRAPA (User Vecter)
    (void*) INT_TRAPA36,
// 37 TRAPA (User Vecter)
    (void*) INT_TRAPA37,
// 38 TRAPA (User Vecter)
    (void*) INT_TRAPA38,
// 39 TRAPA (User Vecter)
    (void*) INT_TRAPA39,
// 40 TRAPA (User Vecter)
    (void*) INT_TRAPA40,
// 41 TRAPA (User Vecter)
    (void*) INT_TRAPA41,
// 42 TRAPA (User Vecter)
    (void*) INT_TRAPA42,
// 43 TRAPA (User Vecter)
    (void*) INT_TRAPA43,
// 44 TRAPA (User Vecter)
    (void*) INT_TRAPA44,
// 45 TRAPA (User Vecter)
    (void*) INT_TRAPA45,
// 46 TRAPA (User Vecter)
    (void*) INT_TRAPA46,
// 47 TRAPA (User Vecter)
    (void*) INT_TRAPA47,
// 48 TRAPA (User Vecter)
    (void*) INT_TRAPA48,
// 49 TRAPA (User Vecter)
    (void*) INT_TRAPA49,
// 50 TRAPA (User Vecter)
    (void*) INT_TRAPA50,
// 51 TRAPA (User Vecter)
    (void*) INT_TRAPA51,
// 52 TRAPA (User Vecter)
    (void*) INT_TRAPA52,
// 53 TRAPA (User Vecter)
    (void*) INT_TRAPA53,
// 54 TRAPA (User Vecter)
    (void*) INT_TRAPA54,
// 55 TRAPA (User Vecter)
    (void*) INT_TRAPA55,
// 56 TRAPA (User Vecter)
    (void*) INT_TRAPA56,
// 57 TRAPA (User Vecter)
    (void*) INT_TRAPA57,
// 58 TRAPA (User Vecter)
    (void*) INT_TRAPA58,
// 59 TRAPA (User Vecter)
    (void*) INT_TRAPA59,
// 60 TRAPA (User Vecter)
    (void*) INT_TRAPA60,
// 61 TRAPA (User Vecter)
    (void*) INT_TRAPA61,
// 62 TRAPA (User Vecter)
    (void*) INT_TRAPA62,
// 63 TRAPA (User Vecter)
    (void*) INT_TRAPA63,
// 64 Interrupt IRQ0
    (void*) INT_IRQ0,
// 65 Interrupt IRQ1
    (void*) INT_IRQ1,
// 66 Interrupt IRQ2
    (void*) INT_IRQ2,
// 67 Interrupt IRQ3
    (void*) INT_IRQ3,
// 68 Interrupt IRQ4
    (void*) INT_IRQ4,
// 69 Interrupt IRQ5
    (void*) INT_IRQ5,
// 70 Interrupt IRQ6
    (void*) INT_IRQ6,
// 71 Interrupt IRQ7
    (void*) INT_IRQ7,
// 72 DMAC0 DEI0
    (void*) INT_DMAC0_DEI0,
// 73 Reserved
    (void*) Dummy,
// 74 DMAC1 DEI1
    (void*) INT_DMAC1_DEI1,
// 75 Reserved
    (void*) Dummy,
// 76 DMAC2 DEI2
    (void*) INT_DMAC2_DEI2,
// 77 Reserved
    (void*) Dummy,
// 78 DMAC3 DEI3
    (void*) INT_DMAC3_DEI3,
// 79 Reserved
    (void*) Dummy,
// 80 ATU01 ITV0-2
    (void*) INT_ATU01_ITV,
// 81 Reserved
    (void*) Dummy,
// 82 Reserved
    (void*) Dummy,
// 83 Reserved
    (void*) Dummy,
// 84 ATU02 ICI0A
    (void*) INT_ATU02_ICI0A,
// 85 Reserved
    (void*) Dummy,
// 86 ATU02 ICI0B
    (void*) INT_ATU02_ICI0B,
// 87 Reserved
    (void*) Dummy,
// 88 ATU03 ICI0C
    (void*) INT_ATU03_ICI0C,
// 89 Reserved
    (void*) Dummy,
// 90 ATU03 ICI0D
    (void*) INT_ATU03_ICI0D,
// 91 Reserved
    (void*) Dummy,
// 92 ATU04 OVI0
    (void*) INT_ATU04_OVI0,
// 93 Reserved
    (void*) Dummy,
// 94 Reserved
    (void*) Dummy,
// 95 Reserved
    (void*) Dummy,
// 96 ATU11 IMI1AA/CMI1BA
    (void*) INT_ATU11_IMI1AA,
// 97 ATU11 IMI1AB
    (void*) INT_ATU11_IMI1AB,
// 98 ATU11 IMI1AC
    (void*) INT_ATU11_IMI1AC,
// 99 ATU11 IMI1AD
    (void*) INT_ATU11_IMI1AD,
// 100 ATU12 IMI1AE
    (void*) INT_ATU12_IMI1AE,
// 101 ATU12 IMI1AF
    (void*) INT_ATU12_IMI1AF,
// 102 ATU12 IMI1AG
    (void*) INT_ATU12_IMI1AG,
// 103 ATU12 IMI1AH
    (void*) INT_ATU12_IMI1AH,
// 104 ATU13 OVI1A-OVI1B
    (void*) INT_ATU13_OVI1,
// 105 Reserved
    (void*) Dummy,
// 106 Reserved
    (void*) Dummy,
// 107 Reserved
    (void*) Dummy,
// 108 ATU21 IMI2A
    (void*) INT_ATU21_IMI2A,
// 109 ATU21 IMI2B
    (void*) INT_ATU21_IMI2B,
// 110 ATU21 IMI2C
    (void*) INT_ATU21_IMI2C,
// 111 ATU21 IMI2D
    (void*) INT_ATU21_IMI2D,
// 112 ATU22 IMI2E
    (void*) INT_ATU22_IMI2E,
// 113 ATU22 IMI2F
    (void*) INT_ATU22_IMI2F,
// 114 ATU22 IMI2G
    (void*) INT_ATU22_IMI2G,
// 115 ATU22 IMI2H
    (void*) INT_ATU22_IMI2H,
// 116 ATU23 OVI2A-OVI2B
    (void*) INT_ATU23_OVI2,
// 117 Reserved
    (void*) Dummy,
// 118 Reserved
    (void*) Dummy,
// 119 Reserved
    (void*) Dummy,
// 120 ATU31 IMI3A
    (void*) INT_ATU31_IMI3A,
// 121 ATU31 IMI3B
    (void*) INT_ATU31_IMI3B,
// 122 ATU31 IMI3C
    (void*) INT_ATU31_IMI3C,
// 123 ATU31 IMI3D
    (void*) INT_ATU31_IMI3D,
// 124 ATU32 OVI3
    (void*) INT_ATU32_OVI3,
// 125 Reserved
    (void*) Dummy,
// 126 Reserved
    (void*) Dummy,
// 127 Reserved
    (void*) Dummy,
// 128 ATU41 IMI4A
    (void*) INT_ATU41_IMI4A,
// 129 ATU41 IMI4B
    (void*) INT_ATU41_IMI4B,
// 130 ATU41 IMI4C
    (void*) INT_ATU41_IMI4C,
// 131 ATU41 IMI4D
    (void*) INT_ATU41_IMI4D,
// 132 ATU42 OVI4
    (void*) INT_ATU42_OVI4,
// 133 Reserved
    (void*) Dummy,
// 134 Reserved
    (void*) Dummy,
// 135 Reserved
    (void*) Dummy,
// 136 ATU51 IMI5A
    (void*) INT_ATU51_IMI5A,
// 137 ATU51 IMI5B
    (void*) INT_ATU51_IMI5B,
// 138 ATU51 IMI5C
    (void*) INT_ATU51_IMI5C,
// 139 ATU51 IMI5D
    (void*) INT_ATU51_IMI5D,
// 140 ATU52 OVI5
    (void*) INT_ATU52_OVI5,
// 141 Reserved
    (void*) Dummy,
// 142 Reserved
    (void*) Dummy,
// 143 Reserved
    (void*) Dummy,
// 144 ATU6 IMI6A
    (void*) INT_ATU6_IMI6A,
// 145 ATU6 IMI6B
    (void*) INT_ATU6_IMI6B,
// 146 ATU6 IMI6C
    (void*) INT_ATU6_IMI6C,
// 147 ATU6 IMI6D
    (void*) INT_ATU6_IMI6D,
// 148 ATU7 IMI7A
    (void*) INT_ATU7_IMI7A,
// 149 ATU7 IMI7B
    (void*) INT_ATU7_IMI7B,
// 150 ATU7 IMI7C
    (void*) INT_ATU7_IMI7C,
// 151 ATU7 IMI7D
    (void*) INT_ATU7_IMI7D,
// 152 ATU81 OSI8A
    (void*) INT_ATU81_OSI8A,
// 153 ATU81 OSI8B
    (void*) INT_ATU81_OSI8B,
// 154 ATU81 OSI8C
    (void*) INT_ATU81_OSI8C,
// 155 ATU81 OSI8D
    (void*) INT_ATU81_OSI8D,
// 156 ATU82 OSI8E
    (void*) INT_ATU82_OSI8E,
// 157 ATU82 OSI8F
    (void*) INT_ATU82_OSI8F,
// 158 ATU82 OSI8G
    (void*) INT_ATU82_OSI8G,
// 159 ATU82 OSI8H
    (void*) INT_ATU82_OSI8H,
// 160 ATU83 OSI8I
    (void*) INT_ATU83_OSI8I,
// 161 ATU83 OSI8J
    (void*) INT_ATU83_OSI8J,
// 162 ATU83 OSI8K
    (void*) INT_ATU83_OSI8K,
// 163 ATU83 OSI8L
    (void*) INT_ATU83_OSI8L,
// 164 ATU84 OSI8M
    (void*) INT_ATU84_OSI8M,
// 165 ATU84 OSI8N
    (void*) INT_ATU84_OSI8N,
// 166 ATU84 OSI8O
    (void*) INT_ATU84_OSI8O,
// 167 ATU84 OSI8P
    (void*) INT_ATU84_OSI8P,
// 168 ATU91 CMI9A
    (void*) INT_ATU91_CMI9A,
// 169 ATU91 CMI9B
    (void*) INT_ATU91_CMI9B,
// 170 ATU91 CMI9C
    (void*) INT_ATU91_CMI9C,
// 171 ATU91 CMI9D
    (void*) INT_ATU91_CMI9D,
// 172 ATU92 CMI9E
    (void*) INT_ATU92_CMI9E,
// 173 Reserved
    (void*) Dummy,
// 174 ATU92 CMI9F
    (void*) INT_ATU92_CMI9F,
// 175 Reserved
    (void*) Dummy,
// 176 ATU101 CMI10A
    (void*) INT_ATU101_CMI10A,
// 177 Reserved
    (void*) Dummy,
// 178 ATU101 CMI10B
    (void*) INT_ATU101_CMI10B,
// 179 Reserved
    (void*) Dummy,
// 180 ATU102 IMI10AG
    (void*) INT_ATU102_IMI10AG,
// 181 Reserved
    (void*) Dummy,
// 182 Reserved
    (void*) Dummy,
// 183 Reserved
    (void*) Dummy,
// 184 ATU11 IMI11A
    (void*) INT_ATU11_IMI11A,
// 185 Reserved
    (void*) Dummy,
// 186 ATU11 IMI11B
    (void*) INT_ATU11_IMI11B,
// 187 ATU11 OVI1
    (void*) INT_ATU11_OVI1,
// 188 CMT0 CMTI0
    (void*) INT_CMT0_CMTI0,
// 189 Reserved
    (void*) Dummy,
// 190 A/D0 ADI0
    (void*) INT_ADI0,
// 191 Reserved
    (void*) Dummy,
// 192 CMT1 CMTI1
    (void*) INT_CMT1_CMTI1,
// 193 Reserved
    (void*) Dummy,
// 194 A/D1 ADI1
    (void*) INT_AD1_ADI1,
// 195 Reserved
    (void*) Dummy,
// 196 A/D2 ADI2
    (void*) INT_AD2_ADI2,
// 197 Reserved
    (void*) Dummy,
// 198 Reserved
    (void*) Dummy,
// 199 Reserved
    (void*) Dummy,
// 200 SCI0 ERI0
    (void*) INT_SCI0_ERI0,
// 201 SCI0 RXI0
    (void*) INT_SCI0_RXI0,
// 202 SCI0 TXI0
    (void*) INT_SCI0_TXI0,
// 203 SCI0 TEI0
    (void*) INT_SCI0_TEI0,
// 204 SCI1 ERI1
    (void*) INT_SCI1_ERI1,
// 205 SCI1 RXI1
    (void*) INT_SCI1_RXI1,
// 206 SCI1 TXI1
    (void*) INT_SCI1_TXI1,
// 207 SCI1 TEI1
    (void*) INT_SCI1_TEI1,
// 208 SCI2 ERI2
    (void*) INT_SCI2_ERI2,
// 209 SCI2 RXI2
    (void*) INT_SCI2_RXI2,
// 210 SCI2 TXI2
    (void*) INT_SCI2_TXI2,
// 211 SCI2 TEI2
    (void*) INT_SCI2_TEI2,
// 212 SCI3 ERI3
    (void*) INT_SCI3_ERI3,
// 213 SCI3 RXI3
    (void*) INT_SCI3_RXI3,
// 214 SCI3 TXI3
    (void*) INT_SCI3_TXI3,
// 215 SCI3 TEI3
    (void*) INT_SCI3_TEI3,
// 216 SCI4 ERI4
    (void*) INT_SCI4_ERI4,
// 217 SCI4 RXI4
    (void*) INT_SCI4_RXI4,
// 218 SCI4 TXI4
    (void*) INT_SCI4_TXI4,
// 219 SCI4 TEI4
    (void*) INT_SCI4_TEI4,
// 220 HCAN0 ERS0
    (void*) INT_HCAN0_ERS0,
// 221 HCAN0 OVR0
    (void*) INT_HCAN0_OVR0,
// 222 HCAN0 RM0
    (void*) INT_HCAN0_RM0,
// 223 HCAN0 SLE0
    (void*) INT_HCAN0_SLE0,
// 224 WDT ITI
    (void*) INT_WDT_ITI,
// 225 Reserved
    (void*) Dummy,
// 226 Reserved
    (void*) Dummy,
// 227 Reserved
    (void*) Dummy,
// 228 HCAN1 ERS1
    (void*) INT_HCAN1_ERS1,
// 229 HCAN1 OVR1
    (void*) INT_HCAN1_OVR1,
// 230 HCAN1 RM1
    (void*) INT_HCAN1_RM1,
// 231 HCAN1 SLE1
    (void*) INT_HCAN1_SLE1,
// 232 Reserved
    (void*) Dummy,
// 233 Reserved
    (void*) Dummy,
// 234 Reserved
    (void*) Dummy,
// 235 Reserved
    (void*) Dummy,
// 236 Reserved
    (void*) Dummy,
// 237 Reserved
    (void*) Dummy,
// 238 Reserved
    (void*) Dummy,
// 239 Reserved
    (void*) Dummy,
// 240 Reserved
    (void*) Dummy,
// 241 Reserved
    (void*) Dummy,
// 242 Reserved
    (void*) Dummy,
// 243 Reserved
    (void*) Dummy,
// 244 Reserved
    (void*) Dummy,
// 245 Reserved
    (void*) Dummy,
// 246 Reserved
    (void*) Dummy,
// 247 Reserved
    (void*) Dummy,
// 248 Reserved
    (void*) Dummy,
// 249 Reserved
    (void*) Dummy,
// 250 Reserved
    (void*) Dummy,
// 251 Reserved
    (void*) Dummy,
// 252 Reserved
    (void*) Dummy,
// 253 Reserved
    (void*) Dummy,
// 254 Reserved
    (void*) Dummy,
// 255 Reserved
    (void*) Dummy
};
*/