/***********************************************************************/
/*                                                                     */
/*  FILE        :vect.h                                                */
/*  DATE        :Wed, Apr 30, 2003                                     */
/*  DESCRIPTION :Definition of Vector                                  */
/*  CPU TYPE    :SH7055F                                               */
/*                                                                     */
/*  This file is generated by Hitachi Project Generator (Ver.1.2).     */
/*                                                                     */
/***********************************************************************/
                  




//;<<VECTOR DATA START (POWER ON RESET)>>
//;0 Power On Reset PC
extern void PowerON_Reset_PC(void);                                                                                                                

//;<<VECTOR DATA END (POWER ON RESET)>>
// 1 Power On Reset SP
extern void *PowerON_Reset_SP;

//;<<VECTOR DATA START (MANUAL RESET)>>
//;2 Manual Reset PC
extern void Manual_Reset_PC(void);                                                                                                                 

//;<<VECTOR DATA END (MANUAL RESET)>>
// 3 Manual Reset SP
extern void *Manual_Reset_SP;

// 4 Illegal code
#pragma interrupt INT_Illegal_code
extern void INT_Illegal_code(void);

// 5 Reserved

// 6 Illegal slot
#pragma interrupt INT_Illegal_slot
extern void INT_Illegal_slot(void);

// 7 Reserved

// 8 Reserved

// 9 CPU Address error
#pragma interrupt INT_CPU_Address
extern void INT_CPU_Address(void);

// 10 DMAC Address error
#pragma interrupt INT_DMAC_Address
extern void INT_DMAC_Address(void);

// 11 NMI
#pragma interrupt INT_NMI
extern void INT_NMI(void);

// 12 User breakpoint trap
#pragma interrupt INT_User_Break
extern void INT_User_Break(void);

// 13 FPU
#pragma interrupt INT_FPU
extern void INT_FPU(void);

// 14 H-UDI
#pragma interrupt INT_HUDI
extern void INT_HUDI(void);

// 15 Reserved

// 16 Reserved

// 17 Reserved

// 18 Reserved

// 19 Reserved

// 20 Reserved

// 21 Reserved

// 22 Reserved

// 23 Reserved

// 24 Reserved

// 25 Reserved

// 26 Reserved

// 27 Reserved

// 28 Reserved

// 29 Reserved

// 30 Reserved

// 31 Reserved

// 32 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA32
extern void INT_TRAPA32(void);

// 33 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA33
extern void INT_TRAPA33(void);

// 34 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA34
extern void INT_TRAPA34(void);

// 35 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA35
extern void INT_TRAPA35(void);

// 36 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA36
extern void INT_TRAPA36(void);

// 37 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA37
extern void INT_TRAPA37(void);

// 38 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA38
extern void INT_TRAPA38(void);

// 39 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA39
extern void INT_TRAPA39(void);

// 40 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA40
extern void INT_TRAPA40(void);

// 41 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA41
extern void INT_TRAPA41(void);

// 42 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA42
extern void INT_TRAPA42(void);

// 43 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA43
extern void INT_TRAPA43(void);

// 44 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA44
extern void INT_TRAPA44(void);

// 45 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA45
extern void INT_TRAPA45(void);

// 46 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA46
extern void INT_TRAPA46(void);

// 47 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA47
extern void INT_TRAPA47(void);

// 48 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA48
extern void INT_TRAPA48(void);

// 49 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA49
extern void INT_TRAPA49(void);

// 50 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA50
extern void INT_TRAPA50(void);

// 51 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA51
extern void INT_TRAPA51(void);

// 52 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA52
extern void INT_TRAPA52(void);

// 53 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA53
extern void INT_TRAPA53(void);

// 54 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA54
extern void INT_TRAPA54(void);

// 55 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA55
extern void INT_TRAPA55(void);

// 56 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA56
extern void INT_TRAPA56(void);

// 57 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA57
extern void INT_TRAPA57(void);

// 58 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA58
extern void INT_TRAPA58(void);

// 59 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA59
extern void INT_TRAPA59(void);

// 60 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA60
extern void INT_TRAPA60(void);

// 61 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA61
extern void INT_TRAPA61(void);

// 62 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA62
extern void INT_TRAPA62(void);

// 63 TRAPA (User Vecter)
#pragma interrupt INT_TRAPA63
extern void INT_TRAPA63(void);

// 64 Interrupt IRQ0
#pragma interrupt INT_IRQ0
extern void INT_IRQ0(void);

// 65 Interrupt IRQ1
#pragma interrupt INT_IRQ1
extern void INT_IRQ1(void);

// 66 Interrupt IRQ2
#pragma interrupt INT_IRQ2
extern void INT_IRQ2(void);

// 67 Interrupt IRQ3
#pragma interrupt INT_IRQ3
extern void INT_IRQ3(void);

// 68 Interrupt IRQ4
#pragma interrupt INT_IRQ4
extern void INT_IRQ4(void);

// 69 Interrupt IRQ5
#pragma interrupt INT_IRQ5
extern void INT_IRQ5(void);

// 70 Interrupt IRQ6
#pragma interrupt INT_IRQ6
extern void INT_IRQ6(void);

// 71 Interrupt IRQ7
#pragma interrupt INT_IRQ7
extern void INT_IRQ7(void);

// 72 DMAC0 DEI0
#pragma interrupt INT_DMAC0_DEI0
extern void INT_DMAC0_DEI0(void);

// 73 Reserved

// 74 DMAC1 DEI1
#pragma interrupt INT_DMAC1_DEI1
extern void INT_DMAC1_DEI1(void);

// 75 Reserved

// 76 DMAC2 DEI2
#pragma interrupt INT_DMAC2_DEI2
extern void INT_DMAC2_DEI2(void);

// 77 Reserved

// 78 DMAC3 DEI3
#pragma interrupt INT_DMAC3_DEI3
extern void INT_DMAC3_DEI3(void);

// 79 Reserved

// 80 ATU01 ITV0-2
#pragma interrupt INT_ATU01_ITV
extern void INT_ATU01_ITV(void);

// 81 Reserved

// 82 Reserved

// 83 Reserved

// 84 ATU02 ICI0A
#pragma interrupt INT_ATU02_ICI0A
extern void INT_ATU02_ICI0A(void);

// 85 Reserved

// 86 ATU02 ICI0B
#pragma interrupt INT_ATU02_ICI0B
extern void INT_ATU02_ICI0B(void);

// 87 Reserved

// 88 ATU03 ICI0C
#pragma interrupt INT_ATU03_ICI0C
extern void INT_ATU03_ICI0C(void);

// 89 Reserved

// 90 ATU03 ICI0D
#pragma interrupt INT_ATU03_ICI0D
extern void INT_ATU03_ICI0D(void);

// 91 Reserved

// 92 ATU04 OVI0
#pragma interrupt INT_ATU04_OVI0
extern void INT_ATU04_OVI0(void);

// 93 Reserved

// 94 Reserved

// 95 Reserved

// 96 ATU11 IMI1AA/CMI1BA
#pragma interrupt INT_ATU11_IMI1AA
extern void INT_ATU11_IMI1AA(void);

// 97 ATU11 IMI1AB
#pragma interrupt INT_ATU11_IMI1AB
extern void INT_ATU11_IMI1AB(void);

// 98 ATU11 IMI1AC
#pragma interrupt INT_ATU11_IMI1AC
extern void INT_ATU11_IMI1AC(void);

// 99 ATU11 IMI1AD
#pragma interrupt INT_ATU11_IMI1AD
extern void INT_ATU11_IMI1AD(void);

// 100 ATU12 IMI1AE
#pragma interrupt INT_ATU12_IMI1AE
extern void INT_ATU12_IMI1AE(void);

// 101 ATU12 IMI1AF
#pragma interrupt INT_ATU12_IMI1AF
extern void INT_ATU12_IMI1AF(void);

// 102 ATU12 IMI1AG
#pragma interrupt INT_ATU12_IMI1AG
extern void INT_ATU12_IMI1AG(void);

// 103 ATU12 IMI1AH
#pragma interrupt INT_ATU12_IMI1AH
extern void INT_ATU12_IMI1AH(void);

// 104 ATU13 OVI1A-OVI1B
#pragma interrupt INT_ATU13_OVI1
extern void INT_ATU13_OVI1(void);

// 105 Reserved

// 106 Reserved

// 107 Reserved

// 108 ATU21 IMI2A
#pragma interrupt INT_ATU21_IMI2A
extern void INT_ATU21_IMI2A(void);

// 109 ATU21 IMI2B
#pragma interrupt INT_ATU21_IMI2B
extern void INT_ATU21_IMI2B(void);

// 110 ATU21 IMI2C
#pragma interrupt INT_ATU21_IMI2C
extern void INT_ATU21_IMI2C(void);

// 111 ATU21 IMI2D
#pragma interrupt INT_ATU21_IMI2D
extern void INT_ATU21_IMI2D(void);

// 112 ATU22 IMI2E
#pragma interrupt INT_ATU22_IMI2E
extern void INT_ATU22_IMI2E(void);

// 113 ATU22 IMI2F
#pragma interrupt INT_ATU22_IMI2F
extern void INT_ATU22_IMI2F(void);

// 114 ATU22 IMI2G
#pragma interrupt INT_ATU22_IMI2G
extern void INT_ATU22_IMI2G(void);

// 115 ATU22 IMI2H
#pragma interrupt INT_ATU22_IMI2H
extern void INT_ATU22_IMI2H(void);

// 116 ATU23 OVI2A-OVI2B
#pragma interrupt INT_ATU23_OVI2
extern void INT_ATU23_OVI2(void);

// 117 Reserved

// 118 Reserved

// 119 Reserved

// 120 ATU31 IMI3A
#pragma interrupt INT_ATU31_IMI3A
extern void INT_ATU31_IMI3A(void);

// 121 ATU31 IMI3B
#pragma interrupt INT_ATU31_IMI3B
extern void INT_ATU31_IMI3B(void);

// 122 ATU31 IMI3C
#pragma interrupt INT_ATU31_IMI3C
extern void INT_ATU31_IMI3C(void);

// 123 ATU31 IMI3D
#pragma interrupt INT_ATU31_IMI3D
extern void INT_ATU31_IMI3D(void);

// 124 ATU32 OVI3
#pragma interrupt INT_ATU32_OVI3
extern void INT_ATU32_OVI3(void);

// 125 Reserved

// 126 Reserved

// 127 Reserved

// 128 ATU41 IMI4A
#pragma interrupt INT_ATU41_IMI4A
extern void INT_ATU41_IMI4A(void);

// 129 ATU41 IMI4B
#pragma interrupt INT_ATU41_IMI4B
extern void INT_ATU41_IMI4B(void);

// 130 ATU41 IMI4C
#pragma interrupt INT_ATU41_IMI4C
extern void INT_ATU41_IMI4C(void);

// 131 ATU41 IMI4D
#pragma interrupt INT_ATU41_IMI4D
extern void INT_ATU41_IMI4D(void);

// 132 ATU42 OVI4
#pragma interrupt INT_ATU42_OVI4
extern void INT_ATU42_OVI4(void);

// 133 Reserved

// 134 Reserved

// 135 Reserved

// 136 ATU51 IMI5A
#pragma interrupt INT_ATU51_IMI5A
extern void INT_ATU51_IMI5A(void);

// 137 ATU51 IMI5B
#pragma interrupt INT_ATU51_IMI5B
extern void INT_ATU51_IMI5B(void);

// 138 ATU51 IMI5C
#pragma interrupt INT_ATU51_IMI5C
extern void INT_ATU51_IMI5C(void);

// 139 ATU51 IMI5D
#pragma interrupt INT_ATU51_IMI5D
extern void INT_ATU51_IMI5D(void);

// 140 ATU52 OVI5
#pragma interrupt INT_ATU52_OVI5
extern void INT_ATU52_OVI5(void);

// 141 Reserved

// 142 Reserved

// 143 Reserved

// 144 ATU6 IMI6A
#pragma interrupt INT_ATU6_IMI6A
extern void INT_ATU6_IMI6A(void);

// 145 ATU6 IMI6B
#pragma interrupt INT_ATU6_IMI6B
extern void INT_ATU6_IMI6B(void);

// 146 ATU6 IMI6C
#pragma interrupt INT_ATU6_IMI6C
extern void INT_ATU6_IMI6C(void);

// 147 ATU6 IMI6D
#pragma interrupt INT_ATU6_IMI6D
extern void INT_ATU6_IMI6D(void);

// 148 ATU7 IMI7A
#pragma interrupt INT_ATU7_IMI7A
extern void INT_ATU7_IMI7A(void);

// 149 ATU7 IMI7B
#pragma interrupt INT_ATU7_IMI7B
extern void INT_ATU7_IMI7B(void);

// 150 ATU7 IMI7C
#pragma interrupt INT_ATU7_IMI7C
extern void INT_ATU7_IMI7C(void);

// 151 ATU7 IMI7D
#pragma interrupt INT_ATU7_IMI7D
extern void INT_ATU7_IMI7D(void);

// 152 ATU81 OSI8A
#pragma interrupt INT_ATU81_OSI8A
extern void INT_ATU81_OSI8A(void);

// 153 ATU81 OSI8B
#pragma interrupt INT_ATU81_OSI8B
extern void INT_ATU81_OSI8B(void);

// 154 ATU81 OSI8C
#pragma interrupt INT_ATU81_OSI8C
extern void INT_ATU81_OSI8C(void);

// 155 ATU81 OSI8D
#pragma interrupt INT_ATU81_OSI8D
extern void INT_ATU81_OSI8D(void);

// 156 ATU82 OSI8E
#pragma interrupt INT_ATU82_OSI8E
extern void INT_ATU82_OSI8E(void);

// 157 ATU82 OSI8F
#pragma interrupt INT_ATU82_OSI8F
extern void INT_ATU82_OSI8F(void);

// 158 ATU82 OSI8G
#pragma interrupt INT_ATU82_OSI8G
extern void INT_ATU82_OSI8G(void);

// 159 ATU82 OSI8H
#pragma interrupt INT_ATU82_OSI8H
extern void INT_ATU82_OSI8H(void);

// 160 ATU83 OSI8I
#pragma interrupt INT_ATU83_OSI8I
extern void INT_ATU83_OSI8I(void);

// 161 ATU83 OSI8J
#pragma interrupt INT_ATU83_OSI8J
extern void INT_ATU83_OSI8J(void);

// 162 ATU83 OSI8K
#pragma interrupt INT_ATU83_OSI8K
extern void INT_ATU83_OSI8K(void);

// 163 ATU83 OSI8L
#pragma interrupt INT_ATU83_OSI8L
extern void INT_ATU83_OSI8L(void);

// 164 ATU84 OSI8M
#pragma interrupt INT_ATU84_OSI8M
extern void INT_ATU84_OSI8M(void);

// 165 ATU84 OSI8N
#pragma interrupt INT_ATU84_OSI8N
extern void INT_ATU84_OSI8N(void);

// 166 ATU84 OSI8O
#pragma interrupt INT_ATU84_OSI8O
extern void INT_ATU84_OSI8O(void);

// 167 ATU84 OSI8P
#pragma interrupt INT_ATU84_OSI8P
extern void INT_ATU84_OSI8P(void);

// 168 ATU91 CMI9A
#pragma interrupt INT_ATU91_CMI9A
extern void INT_ATU91_CMI9A(void);

// 169 ATU91 CMI9B
#pragma interrupt INT_ATU91_CMI9B
extern void INT_ATU91_CMI9B(void);

// 170 ATU91 CMI9C
#pragma interrupt INT_ATU91_CMI9C
extern void INT_ATU91_CMI9C(void);

// 171 ATU91 CMI9D
#pragma interrupt INT_ATU91_CMI9D
extern void INT_ATU91_CMI9D(void);

// 172 ATU92 CMI9E
#pragma interrupt INT_ATU92_CMI9E
extern void INT_ATU92_CMI9E(void);

// 173 Reserved

// 174 ATU92 CMI9F
#pragma interrupt INT_ATU92_CMI9F
extern void INT_ATU92_CMI9F(void);

// 175 Reserved

// 176 ATU101 CMI10A
#pragma interrupt INT_ATU101_CMI10A
extern void INT_ATU101_CMI10A(void);

// 177 Reserved

// 178 ATU101 CMI10B
#pragma interrupt INT_ATU101_CMI10B
extern void INT_ATU101_CMI10B(void);

// 179 Reserved

// 180 ATU102 IMI10AG
#pragma interrupt INT_ATU102_IMI10AG
extern void INT_ATU102_IMI10AG(void);

// 181 Reserved

// 182 Reserved

// 183 Reserved

// 184 ATU11 IMI11A
#pragma interrupt INT_ATU11_IMI11A
extern void INT_ATU11_IMI11A(void);

// 185 Reserved

// 186 ATU11 IMI11B
#pragma interrupt INT_ATU11_IMI11B
extern void INT_ATU11_IMI11B(void);

// 187 ATU11 OVI1
#pragma interrupt INT_ATU11_OVI1
extern void INT_ATU11_OVI1(void);

// 188 CMT0 CMTI0
#pragma interrupt INT_CMT0_CMTI0
extern void INT_CMT0_CMTI0(void);

// 189 Reserved

// 190 A/D0 ADI0
#pragma interrupt INT_ADI0
extern void INT_ADI0(void);

// 191 Reserved

// 192 CMT1 CMTI1
#pragma interrupt INT_CMT1_CMTI1
extern void INT_CMT1_CMTI1(void);

// 193 Reserved

// 194 A/D1 ADI1
#pragma interrupt INT_AD1_ADI1
extern void INT_AD1_ADI1(void);

// 195 Reserved

// 196 A/D2 ADI2
#pragma interrupt INT_AD2_ADI2
extern void INT_AD2_ADI2(void);

// 197 Reserved

// 198 Reserved

// 199 Reserved

// 200 SCI0 ERI0
#pragma interrupt INT_SCI0_ERI0
extern void INT_SCI0_ERI0(void);

// 201 SCI0 RXI0
#pragma interrupt INT_SCI0_RXI0
extern void INT_SCI0_RXI0(void);

// 202 SCI0 TXI0
#pragma interrupt INT_SCI0_TXI0
extern void INT_SCI0_TXI0(void);

// 203 SCI0 TEI0
#pragma interrupt INT_SCI0_TEI0
extern void INT_SCI0_TEI0(void);

// 204 SCI1 ERI1
#pragma interrupt INT_SCI1_ERI1
extern void INT_SCI1_ERI1(void);

// 205 SCI1 RXI1
#pragma interrupt INT_SCI1_RXI1
extern void INT_SCI1_RXI1(void);

// 206 SCI1 TXI1
#pragma interrupt INT_SCI1_TXI1
extern void INT_SCI1_TXI1(void);

// 207 SCI1 TEI1
#pragma interrupt INT_SCI1_TEI1
extern void INT_SCI1_TEI1(void);

// 208 SCI2 ERI2
#pragma interrupt INT_SCI2_ERI2
extern void INT_SCI2_ERI2(void);

// 209 SCI2 RXI2
#pragma interrupt INT_SCI2_RXI2
extern void INT_SCI2_RXI2(void);

// 210 SCI2 TXI2
#pragma interrupt INT_SCI2_TXI2
extern void INT_SCI2_TXI2(void);

// 211 SCI2 TEI2
#pragma interrupt INT_SCI2_TEI2
extern void INT_SCI2_TEI2(void);

// 212 SCI3 ERI3
#pragma interrupt INT_SCI3_ERI3
extern void INT_SCI3_ERI3(void);

// 213 SCI3 RXI3
#pragma interrupt INT_SCI3_RXI3
extern void INT_SCI3_RXI3(void);

// 214 SCI3 TXI3
#pragma interrupt INT_SCI3_TXI3
extern void INT_SCI3_TXI3(void);

// 215 SCI3 TEI3
#pragma interrupt INT_SCI3_TEI3
extern void INT_SCI3_TEI3(void);

// 216 SCI4 ERI4
#pragma interrupt INT_SCI4_ERI4
extern void INT_SCI4_ERI4(void);

// 217 SCI4 RXI4
#pragma interrupt INT_SCI4_RXI4
extern void INT_SCI4_RXI4(void);

// 218 SCI4 TXI4
#pragma interrupt INT_SCI4_TXI4
extern void INT_SCI4_TXI4(void);

// 219 SCI4 TEI4
#pragma interrupt INT_SCI4_TEI4
extern void INT_SCI4_TEI4(void);

// 220 HCAN0 ERS0
#pragma interrupt INT_HCAN0_ERS0
extern void INT_HCAN0_ERS0(void);

// 221 HCAN0 OVR0
#pragma interrupt INT_HCAN0_OVR0
extern void INT_HCAN0_OVR0(void);

// 222 HCAN0 RM0
#pragma interrupt INT_HCAN0_RM0
extern void INT_HCAN0_RM0(void);

// 223 HCAN0 SLE0
#pragma interrupt INT_HCAN0_SLE0
extern void INT_HCAN0_SLE0(void);

// 224 WDT ITI
#pragma interrupt INT_WDT_ITI
extern void INT_WDT_ITI(void);

// 225 Reserved

// 226 Reserved

// 227 Reserved

// 228 HCAN1 ERS1
#pragma interrupt INT_HCAN1_ERS1
extern void INT_HCAN1_ERS1(void);

// 229 HCAN1 OVR1
#pragma interrupt INT_HCAN1_OVR1
extern void INT_HCAN1_OVR1(void);

// 230 HCAN1 RM1
#pragma interrupt INT_HCAN1_RM1
extern void INT_HCAN1_RM1(void);

// 231 HCAN1 SLE1
#pragma interrupt INT_HCAN1_SLE1
extern void INT_HCAN1_SLE1(void);

// 232 Reserved

// 233 Reserved

// 234 Reserved

// 235 Reserved

// 236 Reserved

// 237 Reserved

// 238 Reserved

// 239 Reserved

// 240 Reserved

// 241 Reserved

// 242 Reserved

// 243 Reserved

// 244 Reserved

// 245 Reserved

// 246 Reserved

// 247 Reserved

// 248 Reserved

// 249 Reserved

// 250 Reserved

// 251 Reserved

// 252 Reserved

// 253 Reserved

// 254 Reserved

// 255 Reserved


// Dummy
#pragma interrupt Dummy
extern void Dummy(void);
